`include"mycpu.h"
module mycpu_top(
    input aclk,
    input aresetn,
    //read acquire
    output [ 3:0] arid, //inst: 0, data: 1
    output [31:0] araddr,
    output [ 7:0] arlen, //set to 0
    output [ 2:0] arsize,
    output [ 1:0] arburst, //set to 2'b01
    output [ 1:0] arlock, //set to 0
    output [ 3:0] arcache, //set to 0
    output [ 2:0] arprot,
    output        arvalid,
    input         arready,
    //read
    input  [ 3:0] rid, //inst: 0, data: 1
    input  [31:0] rdata,
    input  [ 1:0] rresp, //ignored
    input         rlast, //ignored
    input         rvalid,
    output         rready,
    //write acquire
    output [ 3:0] awid,
    output [31:0] awaddr,
    output [ 7:0] awlen,
    output [ 2:0] awsize,
    output [ 1:0] awburst, //set to 2'b01
    output [ 1:0] awlock, //set to 0
    output [ 3:0] awcache, //set to 0
    output [ 2:0] awprot, //set to 0
    output        awvalid,
    input         awready,
    //write data
    output [ 3:0] wid, //set to 1
    output [31:0] wdata,
    output [ 3:0] wstrb,
    output        wlast, //set to 1
    output        wvalid,
    input         wready,
    //write feedback
    input  [ 3:0] bid, //ignored
    input  [ 1:0] bresp, //ignored
    input         bvalid,
    output        bready,
    // trace debug interface
    output wire [31:0] debug_wb_pc,
    output wire [ 3:0] debug_wb_rf_we,
    output wire [ 4:0] debug_wb_rf_wnum,
    output wire [31:0] debug_wb_rf_wdata
);
/******************** DECLARATION ********************/
    //cpu data
    wire cpu_data_req;
    wire cpu_data_wr;
    wire [1:0] cpu_data_size;
    wire [31:0] cpu_data_addr;
    wire [3:0] cpu_data_wstrb;
    wire [31:0] cpu_data_wdata;
    wire cpu_data_addr_ok;
    wire cpu_data_data_ok;
    wire [31:0] cpu_data_rdata;
    //cpu inst
    wire cpu_inst_req;
    wire cpu_inst_wr;
    wire [1:0] cpu_inst_size;
    wire [31:0] cpu_inst_addr;
    wire [3:0] cpu_inst_wstrb;
    wire [31:0] cpu_inst_wdata;
    wire cpu_inst_addr_ok;
    wire cpu_inst_data_ok;
    wire [31:0] cpu_inst_rdata;
/******************** CPU CORE ********************/
    mycpu_core u_mycpu_core(
        .clk(aclk),
        .resetn(aresetn),
        //inst sram
        .inst_sram_req(cpu_inst_req),
        .inst_sram_wr(cpu_inst_wr),
        .inst_sram_size(cpu_inst_size),
        .inst_sram_addr(cpu_inst_addr),
        .inst_sram_wstrb(cpu_inst_wstrb),
        .inst_sram_wdata(cpu_inst_wdata),
        .inst_sram_addr_ok(cpu_inst_addr_ok),
        .inst_sram_data_ok(cpu_inst_data_ok),
        .inst_sram_rdata(cpu_inst_rdata),
        //data sram
        .data_sram_req(cpu_data_req),
        .data_sram_wr(cpu_data_wr),
        .data_sram_size(cpu_data_size),
        .data_sram_addr(cpu_data_addr),
        .data_sram_wstrb(cpu_data_wstrb),
        .data_sram_wdata(cpu_data_wdata),
        .data_sram_addr_ok(cpu_data_addr_ok),
        .data_sram_data_ok(cpu_data_data_ok),
        .data_sram_rdata(cpu_data_rdata),
        //debug
        .debug_wb_pc(debug_wb_pc),
        .debug_wb_rf_we(debug_wb_rf_we),
        .debug_wb_rf_wnum(debug_wb_rf_wnum),
        .debug_wb_rf_wdata(debug_wb_rf_wdata)
    );
/******************** AXI BRIDGE ********************/
    axi_bridge u_axi_bridge(
        .clk(aclk),
        .resetn(aresetn),
        /* sram interface */
        //inst sram
        .inst_sram_req(cpu_inst_req),
        .inst_sram_wr(cpu_inst_wr),
        .inst_sram_size(cpu_inst_size),
        .inst_sram_addr(cpu_inst_addr),
        .inst_sram_wstrb(cpu_inst_wstrb),
        .inst_sram_wdata(cpu_inst_wdata),
        .inst_sram_addr_ok(cpu_inst_addr_ok),
        .inst_sram_data_ok(cpu_inst_data_ok),
        .inst_sram_rdata(cpu_inst_rdata),
        //data sram
        .data_sram_req(cpu_data_req),
        .data_sram_wr(cpu_data_wr),
        .data_sram_size(cpu_data_size),
        .data_sram_addr(cpu_data_addr),
        .data_sram_wstrb(cpu_data_wstrb),
        .data_sram_wdata(cpu_data_wdata),
        .data_sram_addr_ok(cpu_data_addr_ok),
        .data_sram_data_ok(cpu_data_data_ok),
        .data_sram_rdata(cpu_data_rdata),
        /* axi interface */
        //read acquire
        .arid(arid),
        .araddr(araddr),
        .arlen(arlen),
        .arsize(arsize),
        .arburst(arburst),
        .arlock(arlock),
        .arcache(arcache),
        .arprot(arprot),
        .arvalid(arvalid),
        .arready(arready),
        //read
        .rid(rid),
        .rdata(rdata),
        .rresp(rresp),
        .rlast(rlast),
        .rvalid(rvalid),
        .rready(rready),
        //write acquire
        .awid(awid),
        .awaddr(awaddr),
        .awlen(awlen),
        .awsize(awsize),
        .awburst(awburst),
        .awlock(awlock),
        .awcache(awcache),
        .awprot(awprot),
        .awvalid(awvalid),
        .awready(awready),
        //write
        .wid(wid),
        .wdata(wdata),
        .wstrb(wstrb),
        .wlast(wlast),
        .wvalid(wvalid),
        .wready(wready),
        //write feedback
        .bid(bid),
        .bresp(bresp),
        .bvalid(bvalid),
        .bready(bready)
    );

endmodule